Table of Contents
Advertisement
Trace Port Interface Unit
17.1
About the TPIU
17.1.1
TPIU block diagrams
17-2
The TPIU is an optional component that acts as a bridge between the on-chip trace data
from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell
(ITM), with separate IDs, to a data stream, encapsulating IDs where required, that is
then captured by a Trace Port Analyzer (TPA).
The TPIU is specially designed for low-cost debug. It is a special version of the
CoreSight TPIU, and you can replace it with CoreSight components if system
requirements demand the additional features of the CoreSight TPIU.
There are two configurations of the TPIU:
•
A configuration that supports ITM debug trace.
•
A configuration that supports both ITM and ETM debug trace.
If the implementation requires no trace support then the TPIU might not be present.
Note
If your Cortex-M3 system uses the optional ETM component, you must use the TPIU
configuration that supports both ITM and ETM debug trace. For a full description of the
ETM, see Chapter 14 Embedded Trace Macrocell.
Figure 17-1 on page 17-3 and Figure 17-2 on page 17-4 show the component layout of
the TPIU for both configurations.
Copyright © 2005-2008 ARM Limited. All rights reserved.
ARM DDI 0337G
Advertisement
Table of Contents
