Activation Levels; Table 5-13 Privilege And Stack Of Different Activation Levels; Table 5-14 Exception Transitions - ARM Cortex-M3 Technical Reference Manual

5.13

Activation levels

Active exception
None
ISR active
Fault handler active
Reset
Active Exception
Reset
a b
ISR or NMI
Fault:
Hard fault
Bus fault
c
No CP fault
Undefined instruction fault
Debug monitor
d
SVC
External interrupt
a. Interrupt service routine.
b. Nonmaskable interrupt.
c. Coprocessor.
d. Software interrupt.
ARM DDI 0337B
When no exceptions are active, the processor is in Thread mode. When an ISR or fault
handler is active, the processor enters Handler mode. Table 5-13 lists the privilege and
stacks of the activation levels.
Activation level
Thread mode
Asynchronous pre-emption level
Synchronous pre-emption level
Thread Mode
Table 5-14 summarizes the transition rules for all exception types and how they relate
to the access rules and stack model.
Triggering event
Reset signal
Set-pending software instruction
or hardware signal
Escalation
Memory access error
Absent CP access
Undefined instruction
Debug event when halting not
enabled
SVC instruction
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 5-13 Privilege and stack of different activation levels

Transition type
Thread
Asynchronous
pre-emption
Synchronous
pre-emption
Synchronous
Privilege Stack
Privileged or user Main or process
Privileged Main
Privileged Main
Privileged Main

Table 5-14 Exception transitions

Privilege
Privileged
or user
Privileged
Privileged
Privileged
Exceptions
Stack
Main or
process
Main
Main
Main
5-31