Table 3-3 Flash Patch Register Summary - ARM Cortex-M3 Technical Reference Manual

System Control
3.1.3 System debug registers
Name
FP_CTRL
FP_REMAP
FP_COMP0
FP_COMP1
FP_COMP2
FP_COMP3
FP_COMP4
FP_COMP5
FP_COMP6
FP_COMP7
PID4
PID5
PID6
PID7
PID0
PID1
3-6
a. Bits [5], [3], [2], [1], [0] are reset by PORESETn. Bit [1] is also reset by SYSRESETn and by
writing a 1 to the VECTRESET bit of the Application Interrupt and Reset Control Register.
b. Bits [16], [17], [18], [19] are also reset by SYSRESETn and by writing a 1 to the VECTRESET
bit of the Application Interrupt and Reset Control Register.
This section lists the system debug registers.
Flash Patch and Breakpoint registers
Table 3-3 gives a summary of the Flash Patch and Breakpoint (FPB) registers. For a
detailed description of the FPB registers, see Chapter 11 System Debug.
Type Address
Read/write 0xE0002000
Read/write
0xE0002004
Read/write
0xE0002008
Read/write
0xE000200C
Read/write
0xE0002010
Read/write
0xE0002014
Read/write 0xE0002018
Read/write 0xE000201C
Read/write
0xE0002020
Read/write
0xE0002024
Read-only
0xE0002FD0
Read-only
0xE0002FD4
Read-only
0xE0002FD8
Read-only
0xE0002FDC
Read-only
0xE0002FE0
Read-only 0xE0002FE4
Copyright © 2005-2008 ARM Limited. All rights reserved.

Table 3-3 Flash patch register summary

Reset value
Bit [0] is reset to 1'b0
-
Bit [0] is reset to 1'b0
Bit [0] is reset to 1'b0
Bit [0] is reset to 1'b0
Bit [0] is reset to 1'b0
Bit [0] is reset to 1'b0
Bit [0] is reset to 1'b0
Bit [0] is reset to 1'b0
Bit [0] is reset to 1'b0
-
-
-
-
-
-
Non-Confidential
Description
Flash Patch Control Register
Flash Patch Remap Register
Flash Patch Comparator Registers
Flash Patch Comparator Registers
Flash Patch Comparator Registers
Flash Patch Comparator Registers
Flash Patch Comparator Registers
Flash Patch Comparator Registers
Flash Patch Comparator Registers
Flash Patch Comparator Registers
Value 0x04
Value 0x00
Value 0x00
Value 0x00
Value 0x03
Value 0xB0
ARM DDI 0337G
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