Table 12-25 Wire Operating Mode, Wiremode, Bit Definitions - ARM Cortex-M3 Technical Reference Manual

Debug Port
12-62
This field is required, and Table 12-25 lists the allowed values of the field, and their
meanings.

Table 12-25 Wire operating mode, WIREMODE, bit definitions

The Read Resend Register, RESEND (SW-DP only)
The Read Resend Register is always present on any SW-DP implementation. Its
purpose is to enable the read data to be recovered from a corrupted debugger transfer,
without repeating the original AP transfer.
It is a 32-bit read-only register at address 0b10 on read operations. Access to the Read
Resend Register is not affected by the value of the CTRLSEL bit in the SELECT
Register.
Performing a read to the RESEND register does not capture new data from the AP. It
returns the value that was returned by the last AP read or DP RDBUFF read.
Reading the RESEND register enables the read data to be recovered from a corrupted
transfer without having to re-issue the original read request or generate a new DAP or
system level access.
The RESEND register can be accessed multiple times. It always returns the same value
until a new access is made to the DP RDBUFF register or to an AP register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
a
WIREMODE Wire operating mode
b00 Reserved
b01 Synchronous (no oversampling).
b1X Reserved.
a. Bits [7:6] of the WCR Register.
ARM DDI 0337B