ARM Cortex-M4 Embedded Processor Manuals

Manuals and User Guides for ARM Cortex-M4 Embedded Processor. We have 1 ARM Cortex-M4 Embedded Processor manual available for free PDF download: Generic User Manual

ARM Cortex-M4 Generic User Manual

ARM Cortex-M4 Generic User Manual (277 pages)

Brand: ARM | Category: Processor | Size: 1.43 MB

Table of Contents

Confidentiality Status
2
Product Status
2
Proprietary Notice
2
Table of Contents
3
Preface

5
- Intended Audience
  6
- Using this Book
  6
- About this Book
  6
  - Typographical Conventions
    7
  - Additional Reading
    8
  - ARM Publications
    8
  - Other Publications
    8
  - Feedback on Content
    9
Chapter 1 Introduction

10
- About the Cortex-M4 Processor and Core Peripherals
  11
Chapter 2 The Cortex-M4 Processor

15
- Programmers Model
  15
  - Processor Mode and Privilege Levels for Software Execution
    15
  - Stacks
    15
  - Core Registers
    16
  - Core Register Set Summary
    16
  - General-Purpose Registers
    17
  - Stack Pointer
    17
  - Link Register
    17
  - Program Counter
    17
  - Application Program Status Register
    18
  - Interrupt Program Status Register
    19
  - Execution Program Status Register
    19
  - Interruptible-Continuable Instructions
    20
  - If-Then Block
    20
  - Thumb State
    20
  - Exception Mask Registers
    20
  - Priority Mask Register
    21
  - Fault Mask Register
    21
  - Base Priority Mask Register
    22
  - CONTROL Register
    22
  - Exceptions and Interrupts
    23
  - Data Types
    23
  - The Cortex Microcontroller Software Interface Standard
    23
- Memory Model
  25
- Exception Model
  34
  - Exception States
    34
  - Exception Types
    34
  - Properties of the Different Exception Types
    35
  - Memmanage
    35
  - Busfault
    35
  - Usagefault
    35
  - Exception Handlers
    36
  - Vector Table
    36
  - Exception Priorities
    37
  - Interrupt Priority Grouping
    38
  - Exception Entry and Return
    38
  - Late-Arriving
    39
  - Exception Entry
    39
  - Exception Return
    41
  - Exception Return Behavior
    41
- Fault Handling
  42
  - Fault Types
    42
  - Fault Escalation and Hard Faults
    43
  - Fault Status Registers and Fault Address Registers
    44
  - Lockup
    44
- Power Management
  45
  - Entering Sleep Mode
    45
  - Wait for Interrupt
    45
  - Wait for Event
    45
  - Wakeup from Sleep Mode
    46
  - Wakeup from WFI or Sleep-On-Exit
    46
  - Wakeup from WFE
    46
  - The Optional Wakeup Interrupt Controller
    46
  - Power Management Programming Hints
    47
  - The Cortex-M4 Instruction Set
    48
Chapter 3 The Cortex-M4 Instruction Set

49
- Instruction Set Summary
  49
- CMSIS Functions
  56
- About the Instruction Descriptions
  58
  - Operands
    59
  - Restrictions When Using PC or SP
    59
  - Flexible Second Operand
    59
  - Instruction Substitution
    60
  - Register with Optional Shift
    60
  - Shift Operations
    60
  - Asr
    60
  - Lsr
    61
  - Lsl
    61
  - Ror
    62
  - Rrx
    62
  - Address Alignment
    64
  - PC-Relative Expressions
    64
  - Conditional Execution
    65
  - The Condition Flags
    66
  - Condition Code Suffixes
    66
  - Absolute Value
    67
  - Compare and Update Value
    67
  - Instruction Width Selection
    68
- Memory Access Instructions
  69
  - Adr
    70
  - Adr{Cond} Rd, Label
    70
  - LDR and STR, Immediate Offset
    71
  - Offset Addressing
    72
  - Pre-Indexed Addressing
    72
  - Post-Indexed Addressing
    72
  - LDR and STR, Register Offset
    74
  - Condition Flags
    75
  - LDR and STR, Unprivileged
    76
  - LDR, PC-Relative
    77
  - LDM and STM
    79
  - PUSH and POP
    81
  - LDREX and STREX
    83
  - Clrex
    85
- General Data Processing Instructions
  86
  - ADD, ADC, SUB, SBC, and RSB
    88
  - AND, ORR, EOR, BIC, and ORN
    91
  - ASR, LSL, LSR, ROR, and RRX
    93
  - Clz
    95
  - Count Leading Zeros
    95
  - CMP and CMN
    96
  - Compare and Compare Negative
    96
  - MOV and MVN
    97
  - Move and Move NOT
    97
  - Movt
    99
  - REV, REV16, REVSH, and RBIT
    100
  - SADD16 and SADD8
    101
  - SHADD16 and SHADD8
    102
  - SHASX and SHSAX
    103
  - SHSUB16 and SHSUB8
    105
  - SSUB16 and SSUB8
    106
  - SASX and SSAX
    107
  - TST and TEQ
    109
  - Test Bits and Test Equivalence
    109
  - UADD16 and UADD8
    110
  - Unsigned Add 16 and Unsigned Add 8
    110
  - UASX and USAX
    111
  - UHADD16 and UHADD8
    113
  - UHASX and UHSAX
    114
  - UHSUB16 and UHSUB8
    116
  - Sel
    117
  - Usad8
    118
  - Usada8
    119
  - USUB16 and USUB8
    120
- Multiply and Divide Instructions
  121
  - MUL, MLA, and MLS
    122
  - Umull, Umaal, Umlal
    124
  - SMLA and SMLAW
    126
  - Smlad
    128
  - Signed Multiply Accumulate Long Dual
    128
  - SMLAL and SMLALD
    129
  - SMLSD and SMLSLD
    131
  - SMMLA and SMMLS
    133
  - Smmul
    135
  - SMUAD and SMUSD
    136
  - SMUL and SMULW
    138
  - UMULL, UMLAL, SMULL, and SMLAL
    140
  - SDIV and UDIV
    141
- Saturating Instructions
  142
  - SSAT and USAT
    143
  - SSAT16 and USAT16
    144
  - QADD and QSUB
    145
  - QASX and QSAX
    147
  - QDADD and QDSUB
    149
  - UQASX and UQSAX
    150
  - UQADD and UQSUB
    152
- Packing and Unpacking Instructions
  154
  - PKHBT and PKHTB
    155
  - SXT and UXT
    157
  - SXTA and UXTA
    159
- Bitfield Instructions
  161
  - BFC and BFI
    162
  - Bit Field Clear and Bit Field Insert
    162
  - SBFX and UBFX
    163
- Branch and Control Instructions
  165
  - B, BL, BX, and BLX
    166
  - CBZ and CBNZ
    168
  - It
    169
  - TBB and TBH
    171
  - Branch Byte and Table Branch Halfword
    171
- Floating-Point Instructions
  173
  - Vabs
    175
  - Floating-Point Absolute
    175
  - Vadd
    176
  - Vcmp, Vcmpe
    177
  - VCVT, VCVTR between Floating-Point and Integer
    178
  - VCVT between Floating-Point and Fixed-Point
    179
  - Vcvtb, Vcvtt
    180
  - VDIV
    181
  - Divides Floating-Point Values
    181
  - Vfma, Vfms
    182
  - Vfnma, Vfnms
    183
  - Vldm
    184
  - Floating-Point Load Multiple
    184
  - Vldr
    185
  - Loads a Single Extension Register from Memory
    185
  - Vlma, Vlms
    186
  - VMOV Immediate
    187
  - Move Floating-Point Immediate
    187
  - VMOV Register
    188
  - Copies the Contents of One Register to Another
    188
  - VMOV Scalar to ARM Core Register
    189
  - VMOV ARM Core Register to Single Precision
    190
  - VMOV Two ARM Core Registers to Two Single Precision
    191
  - VMOV ARM Core Register to Scalar
    192
  - Vmrs
    193
  - Move to ARM Core Register from Floating-Point System Register
    193
  - Vmsr
    194
  - Vmul
    195
  - Vneg
    196
  - Floating-Point Negate
    196
  - Vnmla, Vnmls, Vnmul
    197
  - Vpop
    198
  - Floating-Point Extension Register Pop
    198
  - Vpush
    199
  - Floating-Point Extension Register Push
    199
  - Vsqrt
    200
  - Floating-Point Square Root
    200
  - Vstm
    201
  - Floating-Point Store Multiple
    201
  - Vstr
    202
  - Floating-Point Store
    202
  - Vsub
    203
  - Floating-Point Subtract
    203
- Miscellaneous Instructions
  204
  - Bkpt
    205
  - Breakpoint
    205
  - Cps
    206
  - Change Processor State
    206
  - Dmb
    207
  - Data Memory Barrier
    207
  - Dsb
    208
  - Data Synchronization Barrier
    208
  - Isb
    209
  - Instruction Synchronization Barrier
    209
  - Mrs
    210
  - Msr
    211
  - Nop
    212
  - No Operation
    212
  - Sev
    213
  - Send Event
    213
  - Svc
    214
  - Supervisor Call
    214
  - Wfe
    215
  - Wfi
    216
  - Cortex-M4 Peripherals
    217
- About the Cortex-M4 Peripherals
  218
- Nested Vectored Interrupt Controller
  219
  - Accessing the Cortex-M4 NVIC Registers Using CMSIS
    220
  - Interrupt Set-Enable Registers
    220
  - Interrupt Clear-Enable Registers
    221
  - Interrupt Set-Pending Registers
    221
  - Interrupt Clear-Pending Registers
    222
  - Interrupt Active Bit Registers
    223
  - Interrupt Priority Registers
    223
  - Software Trigger Interrupt Register
    224
  - Level-Sensitive and Pulse Interrupts
    224
  - NVIC Usage Hints and Tips
    225
  - NVIC Programming Hints
    225
  - CMSIS Functions for NVIC Control
    226
  - Auxiliary Control Register
    227
- System Control Block
  227
  - CPUID Base Register
    229
  - Interrupt Control and State Register
    229
  - Vector Table Offset Register
    232
  - Tbloff
    232
  - Application Interrupt and Reset Control Register
    232
  - Binary Point
    234
  - System Control Register
    235
  - Configuration and Control Register
    235
  - System Handler Priority Registers
    237
  - System Handler Priority Register 1
    237
  - System Handler Priority Register 2
    238
  - System Handler Priority Register 3
    238
  - System Handler Control and State Register
    239
  - SHCSR Bit Assignments
    239
  - Configurable Fault Status Register
    240
  - Memmanage Fault Status Register
    241
  - MMFSR Bit Assignments
    241
  - Busfault Status Register
    242
  - BFSR Bit Assignments
    242
  - Usagefault Status Register
    244
  - UFSR Bit Assignments
    244
  - Hardfault Status Register
    246
  - HFSR Bit Assignments
    246
  - Busfault Address Register
    247
  - Auxiliary Fault Status Register
    247
  - System Control Block Usage Hints and Tips
    247
- System Timer, Systick
  249
  - Systick Control and Status Register
    249
  - Systick SYST_CSR Register Bit Assignments
    249
  - Systick Reload Value Register
    250
  - Calculating the RELOAD Value
    250
  - Systick Current Value Register
    251
  - Systick Calibration Value Register
    251
  - SYST_CALIB Register Bit Assignments
    251
  - Systick Usage Hints and Tips
    252
- Optional Memory Protection Unit
  253
  - Memory Attributes Summary
    253
  - MPU Registers Summary
    254
  - MPU Type Register
    254
  - TYPE Register Bit Assignments
    254
  - MPU Control Register
    255
  - MPU_CTRL Register Bit Assignments
    255
  - MPU Region Number Register
    256
  - MPU Region Base Address Register
    256
  - MPU_RNR Bit Assignments
    256
  - MPU_RBAR Bit Assignments
    257
  - MPU Region Attribute and Size Register
    257
  - The ADDR Field
    257
  - MPU_RASR Bit Assignments
    258
  - SIZE Field Values
    258
  - MPU Access Permission Attributes
    259
  - Example SIZE Field Values
    259
  - TEX, C, B, and S Encoding
    259
  - AP Encoding
    260
  - MPU Mismatch
    260
  - Updating an MPU Region
    260
  - Updating an MPU Region Using Separate Words
    260
  - Updating an MPU Region Using Multi-Word Writes
    261
  - Subregions
    262
  - Example of SRD Use
    262
  - MPU Usage Hints and Tips
    262
  - MPU Configuration for a Microcontroller
    263
- Floating Point Unit (FPU)
  264
Appendix A Cortex-M4 Options

269
- Cortex-M4 Implementation Options
  270
  - A-1 Effects of the Cortex-M4 Implementation Options
    270
  - Floating-Point Instructions on Page
    270
Chapter 4 Cortex-M4 Peripherals

269
Glossary

272

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