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ARM DDI 0337B
Successful read operation (OK response)
A successful read operation consists of three phases:
•
an eight-bit read packet request, from the host to the target
•
a three-bit OK acknowledge response, from the target to the host
•
a 33-bit data read phase, where data is transferred from the target to the host.
By default, there are single-cycle turnaround periods between the first and second of
these phases, and after the third phase. See the description of Trn in Key to illustrations
of operations on page 12-22 for more information. However, there is no turnaround
period between the second and third phases.
A successful read operation is shown in Figure 12-9.
WAIT response to Read or Write operation request
A WAIT response to a read or write packet request consists of two phases:
•
an eight-bit read or write packet request, from the host to the target
•
a three-bit WAIT acknowledge response, from the target to the host.
By default, there are single-cycle turnaround periods between these two phases, and
after the second phase. See the description of Trn in Key to illustrations of operations
on page 12-22 for more information.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Figure 12-8 Serial Wire Debug successful write operation
Figure 12-9 Serial Wire Debug successful read operation
Debug Port
12-25
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