Table 12-4 Dpacc And Apacc Ack Responses - ARM Cortex-M3 Technical Reference Manual

Debug Port
Response ACK[2:0] encoding
OK/FAULT b010
WAIT b001
12-12
Operating mode
When the DPACC or APACC instruction is the current instruction in the
IR, the shift section of the DP Access Register or AP Access Register is
selected as the serial path between TDI and TDO:
• In the Capture-DR state, the result of the previous transaction, if
any, is returned, together with a 3-bit ACK response. Only two
ACK responses are implemented, and these are summarized in
Table 12-4.
See:
The OK/FAULT response to a DPACC or APACC access on page 12-13
The WAIT response to a DPACC or APACC access on page 12-15
All other ACC encodings are Reserved.
• In the Shift-DR state, this data is shifted out, least significant bit
first. As shown in Figure 12-6 on page 12-13, the first three bits of
data shifted out are ACK[2:0], and therefore you can check the
ACK response without shifting out all of the returned data, see The
WAIT response to a DPACC or APACC access on page 12-15.
As the returned data is shifted out to TDO, new data is shifted in
from TDI. This is described in The OK/FAULT response to a
DPACC or APACC access on page 12-13.
• Operation in the Update-DR depends on whether the ACK[2:0]
response was OK/FAULT or WAIT. The two cases are described in:
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Table 12-4 DPACC and APACC ACK responses

Update-DR operation following an OK/FAULT response on
page 12-13
Update-DR operation following a WAIT response on
page 12-15.
ARM DDI 0337B