Table 11-5 Flash Patch Comparator Registers Bit Assignments - ARM Cortex-M3 Technical Reference Manual

System Debug
Bits Field
[31:30] REPLACE
[29] -
[28:2] COMP
[1] -
[0] ENABLE
11-12

Table 11-5 Flash Patch Comparator Registers bit assignments

Function
This selects what happens when the COMP address is matched.
It is interpreted as:
b00 = remap to remap address. See FP_REMAP
b01 = set BKPT on lower halfword, upper is unaffected
b10 = set BKPT on upper halfword, lower is unaffected
b11 = set BKPT on both lower and upper halfwords.
Settings other than b00 are only valid for instruction comparators. Literal comparators ignore
non-b00 settings.
Address remapping only takes place for the b00 setting.
Reserved
Comparison address.
Reserved.
Compare and remap enable for Flash Patch Comparator Register n:
1 = Flash Patch Comparator Register n compare and remap enabled
0 = Flash Patch Comparator Register n compare and remap disabled.
The ENABLE bit of FP_CTRL must also be set to enable comparisons.
Reset clears the ENABLE bit.
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