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Bit range
R/W
Field name
[31:17]
-
-
[16]
W
REGWnR
[15:5]
-
-
[4:0]
W
REGSEL
ARM DDI 0337B
Table 10-3 shows the bit functions of the Debug Core Selector Register.
Function
Reserved
Write = 1
Read = 0
-
0b00000 = R0
0b00001 = R1
...
0b01111 = R15
0b10000 = xPSR/ Flags
0b10001 = MSP (Main SP)
0b10010 = PSP (Process SP)
0b10011 = RAZ/WI
0b10100 = CONTROL/FAULTMASK/BASEPRI/PRIMASK (packed into 4 bytes
of words. CONTROL is MSB (31:24)
0b1xxxx = Reserved
This write-only register generates a handshake to the core to transfer data to or from
Debug Core Register Data Register and the selected register. Until this core transaction
is complete, bit [16], S_REGRDY, of the DHCSR is 0.
Note
•
Writes to this register in any size but word are Unpredictable.
•
PSR registers are fully accessible this way, whereas some read as 0 when using
MRS instructions.
•
All bits can be written, but some combinations cause a fault when execution is
resumed.
•
IT might be written and behaves as though in an IT block.
•
ICI can be written, though invalid values or when not used on an LDM/STM
causes a fault, as would on return from exception. Changing ICI from a value to
0 causes the underlying LDM/STM to start, not continue.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Table 10-3 Debug Core Selector Register
Core Debug
10-7
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