Chapter 12 Bus Interface; About Bus Interfaces - ARM Cortex-M3 Technical Reference Manual

Bus Interface
12.1

About bus interfaces

12-2
The processor contains four bus interfaces:
• The ICode memory interface. Instruction fetches from Code memory space
( -
0x0000000 0x1FFFFFFF)
High-performance Bus (AHB)-Lite bus. For more information, see ICode bus
interface on page 12-4.
• The DCode memory interface. Data and debug accesses to Code memory space
( -
0x0000000 0x1FFFFFFF
information, see DCode bus interface on page 12-6.
• The System interface. Instruction fetches, and data and debug accesses, to System
space (
0x20000000 - 0xDFFFFFFF
this 32-bit AHB-Lite bus. For more information, see System interface on
page 12-7.
• The External Private Peripheral Bus (PPB). Data and debug accesses to External
PPB space (
0xE0040000 - 0xE00FFFFF
Peripheral Bus (APB) (AMBA v3.0) bus. The Trace Port Interface Unit (TPIU)
and vendor specific peripherals are on this bus. For more information, see
External private peripheral interface on page 12-10.
Note
The processor contains an internal PPB for accesses to the Nested Vectored Interrupt
Controller (NVIC), Data Watchpoint and Trace (DWT), Instrumentation Trace
Macrocell (ITM), Flash Patch and Breakpoint (FPB), and Memory Protection Unit
(MPU).
Copyright © 2005-2008 ARM Limited. All rights reserved.
are performed over this 32-bit Advanced
) are performed over this 32-bit AHB-Lite bus. For more
,
0xE0100000 - 0xFFFFFFFF
) are performed over this 32-bit Advanced
Non-Confidential
) are performed over
ARM DDI 0337G
Unrestricted Access