Table of Contents
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Preface
About this manual
Product revision status
Intended audience
Using this manual
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This is the Technical Reference Manual (TRM) for the Cortex-M3 processor.
The rnpn identifier indicates the revision status of the product described in this manual,
where:
rn
Identifies the major revision of the product.
pn
Identifies the minor revision or modification status of the product.
This manual is written to help system designers, system integrators, and verification
engineers who are implementing a System-on-a-Chip (SoC) device based on the
Cortex-M3 processor.
This manual is organized into the following chapters:
Chapter 1 Introduction
Read this chapter to learn about the components of the Cortex-M3
processor, and about the processor instruction set.
Chapter 2 Programmer's Model
Read this chapter to learn about the Cortex-M3 register set, modes of
operation, and other information for programming the Cortex-M3
processor.
Chapter 3 System Control
Read this chapter to learn about the registers and programmer's model for
system control.
Chapter 4 Memory Map
Read this chapter to learn about the processor memory map and
bit-banding feature.
Chapter 5 Exceptions
Read this chapter to learn about the processor exception model.
Chapter 6 Clocking and Resets
Read this chapter to learn about the processor clocking and resets.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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