Access Alignment; Table 12-2 Bus Mapper Unaligned Accesses - ARM Cortex-M3 Technical Reference Manual

12.8

Access alignment

Unaligned access Aligned access
Cycle 1
ADDR
Size HSIZE
[1:0]
Halfword 00 Halfword
Halfword 01 Byte
Halfword 10 Halfword
Halfword 11 Byte
Word 00 Word
Word 01 Byte
Word 10 Halfword
Word 11 Byte
ARM DDI 0337G
Unrestricted Access
The processor supports unaligned data accesses using the ARMv6 model. The DCode
and System bus interfaces contain logic that converts unaligned accesses to aligned
accesses.
The unaligned data accesses are described in Table 12-2. The table shows the unaligned
access in the first column, with the remaining columns showing what the access is
converted into. Depending on the size and alignment of the unaligned access, it is
converted into two or three aligned accesses.
Cycle 2
HADDR
HSIZE
[1:0]
00 -
01 Byte
10 -
11 Byte
00 -
01 Halfword
10 Halfword
11 Halfword
Note
Unaligned accesses that cross into the bit-band alias region are not treated as bit-band
requests, and the access is not remapped to the bit-band region. Instead, they are treated
as a halfword or byte access to the bit-band alias region.
Copyright © 2005-2008 ARM Limited. All rights reserved.

Table 12-2 Bus mapper unaligned accesses

HADDR[1:0]
-
10
-
{(Addr+4)[31:2],2b00}
-
10
{(Addr+4)[31:2],2b00}
{(Addr+4)[31:2],2b00}
Non-Confidential
Bus Interface
Cycle 3
HSIZE HADDR[1:0]
- -
- -
- -
- -
- -
Byte {(Addr+4)[31:2],2b00}
- -
Byte {(Addr+4)[31:2],2b10}
12-11