Interrupts And Updating The Mpu - ARM Cortex-M3 Technical Reference Manual

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9.6

Interrupts and updating the MPU

ARM DDI 0337B
An MPU region can contain critical data. This is because it takes more than one bus
transaction to update. This is normally two words. As a result, it is not "thread safe".
That is, an interrupt can split the two words, leaving the region with incoherent
information. There are two different issues:
An interrupt can come in that would also update the MPU. This is not only a
read-modify-write issue, it also affects cases where the interrupt routine is
guaranteed not to modify the same region. This is because the programming relies
on the region number being written into a register so that it knows which region
to update. So, interrupts must be disabled around each update routine in this case.
An interrupt can come in that would use the region being updated or would be
affected because only the base or size fields had been updated. If the new size field
is changed, but the base is not, the base+new_size might overlap into an area
normally handled by another region. In this case, the disable-modify-enable
approach is required.
But, for standard OS context switch code, which would be changing user regions, there
is no risk, as these regions would be preset to be user privilege and a user area address.
This means that even an interrupt would cause no side effect. Therefore the
disable/enable code is not required nor is interrupt disable.
The most common approach is to only program the MPU from two places: boot code
and context switcher. If those are the only two places, and the context switcher is only
updating user regions, then disable is not required because the context switcher is
already a critical region and the boot code runs with interrupts disabled.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Memory Protection Unit
9-19

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