Figure 5-5 Exception Exit Timing - ARM Cortex-M3 Technical Reference Manual

Exceptions
CLK
HADDRI[31:0]
HRDATAI[31:0]
HADDRS[31:0]
HRDATAS[31:0]
CURRPRI[7:0]
ETMINSTAT[2:0]
ETMINTNUM[8:0]
5.8.2 Returning the processor from an ISR
5-18
Last instruction fetch of ISR (BX LR)
000
ETMINSTAT indicates:
• 3'b010 to show that the ISR has exited. ETMINTNUM shows the number of the
ISR that exited.
• 3'b011 in the cycle after interrupt exit if a previous stacked ISR is being returned
to. ETMINTNUM shows the number of the interrupt that is being returned to.
Note
If a higher priority exception occurs during the stack pop, the processor abandons the
stack pop, rewinds the stack pointer, and services the exception as a tail-chain case.
Exception returns occur when one of the following instructions loads a value of
into the PC:
0xFFFFFFFX
• POP/LDM which includes loading the PC
• LDR with PC as a destination
• BX with any register.
Copyright © 2005-2008 ARM Limited. All rights reserved.
PC
PC+4
I0
SP+1C
SP+0 SP+4 SP+8 SP+C
SP+18
PC r0
09
010
34
Non-Confidential
PC+8
I1 I2
SP+10
SP+14
r1 r2 r3
000

Figure 5-5 Exception exit timing

ARM DDI 0337G
PC+16
PC+12
I3
LR
FF
011 000
00
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