Table 12-11 Summary Of Host (Debugger) Responses To The Sw-Dp Acknowledge - ARM Cortex-M3 Technical Reference Manual

Operation ACK
requested received
R OK
W OK
X WAIT
X FAULT
X No ACK
R Invalid
ACK
W Invalid
ACK
a. The host debugger might be able to support corrupted reads, or it might have to re-try the transfer.
b. If overrun detection is enabled, a data phase is required. On a read operation, the RDATA value is Unpredictable and the
debugger must capture and discard this data. On a write operation the debugger must send a WDATA packet, that the target
ignores.
12.3.5 Transfer timings
ARM DDI 0337B
Whenever a debugger issues an operation request to a SW-DP, it expects to receive a
3-bit acknowledgement, as listed in the ACK columns of Table 12-7 on page 12-33 and
Table 12-7 on page 12-33. This section summarizes how the debugger must respond to
this acknowledgement, for all possible cases. This is shown in Table 12-11.

Table 12-11 Summary of host (debugger) responses to the SW-DP acknowledge

Host response
Data phase
Capture RDATA from target and
check for valid parity and protocol.
Send WDATA.
No data phase, unless overrun
b
detection is enabled .
No data phase, unless overrun
b
detection is enabled .
Back off to allow for possible data
phase.
Back off to allow for possible data
phase.
Back off to ensure that target does
not capture next header as
WDATA.
This section describes the interaction between the timing of transactions on the serial
wire interface, and the DAP internal bus transfers. It shows when the target responds
with a WAIT acknowledgement.
Figure 12-15 on page 12-38 shows the effect of signalling ACK = WAIT on the length
of the packet.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Additional action
Might have to re-issue original read request if parity or
protocol fault and unable to flag data as invalid
Validity of this transfer is confirmed on next access.
Normally, repeat the original operation request. See
The WAIT response on page 12-29 for more
information.
Can send new headers, but only an access to DP
register addresses b0X gives a valid response.
Can attempt IDCODE Register read. Otherwise reset
connection and retrain. See Protocol Error responses
on page 12-31.
Can check CTRL/STAT Register to see if the response
sent was OK.
Repeat the write access. A FAULT response is
possible if the first response was sent as OK but not
recognized as valid by the debugger. The subsequent
write is not affected by the first, misread, response.
Debug Port
a
.
12-37