About Bus Interfaces - ARM Cortex-M3 Technical Reference Manual

Bus Interface
14.1

About bus interfaces

14-2
The processor contains four bus interfaces:
• The ICode memory interface. Instruction fetches from Code memory space
( -
0x0000000 0x1FFFFFFF)
information, see ICode bus interface on page 14-3.
• The DCode memory interface. Data and debug accesses to Code memory space
( -
0x0000000 0x1FFFFFFF
information, see DCode bus interface on page 14-5.
• The System interface. Instruction fetches, and data and debug accesses, to System
space (
0x20000000 - 0xDFFFFFFF
this 32-bit AHBLite bus. For more information, see System interface on
page 14-6.
• The External Private Peripheral Bus (PPB). Data and debug accesses to External
PPB space (
0xE0040000 - 0xE00FFFFF
(AMBA v2.0) bus. The Trace Port Interface Unit (TPIU) and vendor specific
peripherals are on this bus. For more information, see External private peripheral
interface on page 14-8.
Note
The processor contains an internal Private Peripheral Bus for accesses to the Nested
Vectored Interrupt Controller (NVIC), Data Watchpoint and Trigger (DWT), Flash
Patch and Breakpoint (FPB), and Memory Protection Unit (MPU).
Copyright © 2005, 2006 ARM Limited. All rights reserved.
are performed over this 32-bit AHBLite bus. For more
) are performed over this 32-bit AHBLite bus. For more
,
0xE0100000 - 0xFFFFFFFF
) are performed over this 32-bit APB
) are performed over
ARM DDI 0337B