Table 11-28 Ahb-Ap Register Summary - ARM Cortex-M3 Technical Reference Manual

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System Debug

Control and Status Word

Transfer Address

Data Read/write

Banked Data 0

Banked Data 1

Banked Data 2

Banked Data 3

Debug ROM Address

Identification Register

AHB-AP Control and Status Word Register

Use this register to configure and control transfers through the AHB interface.

Figure 11-19 shows the bit assignments of the AHB-AP Control and Status Word

Table 11-28 AHB-AP register summary

See Register

See AHB-AP Control and Status Word Register

on page 11-40

See AHB-AP Transfer Address Register on

See AHB-AP Data Read/Write Register on

See AHB-AP Banked Data Registers 0-3 on

See AHB-AP Banked Data Registers 0-3 on

See AHB-AP Banked Data Registers 0-3 on

See AHB-AP Banked Data Registers 0-3 on

See AHB-AP Debug ROM Address Register on

See AHB-AP ID Register on page 11-44

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