Table 5-4 Exception Entry Steps - ARM Cortex-M3 Technical Reference Manual

Action Restartable?
Push eight No.
a
registers
Read vector table Yes. Late-arriving
exception can cause
restart.
Read SP from No.
vector table
Update PC No.
Load pipeline Yes. Pre-emption
reloads pipeline from
new vector table read.
Update LR No.
a. When tail-chaining, this step is skipped.
ARM DDI 0337B
Table 5-4 describes the steps that the Cortex-M3 processor takes before it enters an ISR.
Description
Pushes xPSR, PC, r0, r1, r2, r3, r12, and LR on selected stack.
Reads vector table from memory based on
table base + (exception number 4). Read on the ICode bus can be
done simultaneously with register pushes on the DCode bus.
On Reset only, updates SP to top of stack from vector table. Other
exceptions do not modify SP except to select stack, push, and pop.
Updates PC with vector table read location. Late-arriving exceptions
cannot be processed until the first instruction starts to execute.
Loads instructions from location pointed to by vector table. This is
done in parallel with register push.
LR is set to EXC_RETURN to exit from exception. EXC_RETURN is
one of 16 values as defined in ARMv7-M Architecture Reference
Manual.
Figure 5-2 on page 5-12 shows an example of exception entry timing.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Table 5-4 Exception entry steps

Exceptions
5-11