Table 16-1 Etm Interface Ports; Cpu Etm Interface Port Descriptions - ARM Cortex-M3 Technical Reference Manual

16.2

CPU ETM interface port descriptions

Port name Direction
ETMIVALID Output
ETMIBRANCH Output
ETMIINDBR Output
ETMVALID Output
ETMICCFAIL Output
ETMINTSTAT[2:0] Output
ETMINTNUM[8:0] Output
ARM DDI 0337B
The processor has a port which enables the ETM to determine the instruction execution
sequence. These port descriptions are described in Table 16-1.
Qualified by
-
ETMIVALID
ETMIBRANCH
No qualifier
ETMIVALID
No qualifier
ETMINTSTAT
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Description
Instruction in execute is valid. Marks that an opcode has entered
the first cycle of execute.
Opcode is a branch target. Marks that current code is the
destination of a PC modifying event (branch, interrupt
processing).
Opcode branch target is indirect. Marks that the current opcode
is a branch target whose destination cannot be deduced from the
PC contents. For example, LSU, register move, or interrupt
processing.
Signals that the current data address as seen by the DWT is valid
on this cycle.
Opcode condition code fail or pass. Marks if the current opcode
has failed or passed its conditional execution check. An opcode
is conditionally executed if it is a conditional branch, or for all
other opcode found in an IT block.
Interrupt status. Marks the interrupt status of the current cycle:
000 no status
001 interrupt entry
010 interrupt exit
011 interrupt return
100 - Vector fetch and stack push
ETMINTSTAT Entry/Return is asserted in the first cycle of the
new interrupt context. Exit occurs without ETMIVALID.
Interrupt number. Marks the interrupt number of the current
execution context.
Embedded Trace Macrocell Interface

Table 16-1 ETM interface ports

16-3