ARM Cortex-A53 MPCore Processor Manuals

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ARM Cortex-A53 MPCore Technical Reference Manual

ARM Cortex-A53 MPCore Technical Reference Manual (635 pages)

Brand: ARM | Category: Processor | Size: 4.87 MB

Table of Contents

Table of Contents
3
Preface

6
- About this Book
  7
  - Typographical Conventions
    8
  - Timing Diagrams
    9
  - Other Publications
    10
- Feedback
  11
Chapter 1 Introduction

13
- About the Cortex-A53 Processor
  13
- Compliance
  14
- Features
  16
- Interfaces
  17
- Implementation Options
  18
- Processor Configuration
  19
- Test Features
  20
- Product Documentation and Design Flow
  21
- Product Revisions
  23
Chapter 2 Functional Description

24
- About the Cortex-A53 Processor Functions
  25
- Interfaces
  30
- Clocking and Resets
  32
- Power Management
  39
  - Power Domains
    39
  - Normal State
    41
Chapter 3 Programmers Model

51
- About the Programmers Model
  52
- Armv8-A Architecture Concepts
  54
Chapter 4 System Control

62
- About System Control
  63
- Aarch64 Register Summary
  64
- Aarch64 Register Descriptions
  75
  - Cache Type Register
    108
  - Domain Access Control Register
    153
  - Interrupt Status Register
    184
- Aarch32 Register Summary
  196
- Aarch32 Register Descriptions
  218
- Auxiliary Control Register
  257
Chapter 5 Memory Management Unit

341
- About the MMU
  341
- TLB Organization
  342
- TLB Match Process
  343
- External Aborts
  344
Chapter 6 Level 1 Memory System

346
- About the L1 Memory System
  346
- Cache Behavior
  347
- Support for V8 Memory Types
  350
- L1 Instruction Memory System
  351
- L1 Data Memory System
  353
- Data Prefetching
  356
- Direct Access to Internal Memory
  357
Chapter 7 Level 2 Memory System

367
- About the L2 Memory System
  367
- Snoop Control Unit
  368
- ACE Master Interface
  371
- CHI Master Interface
  378
- Additional Memory Attributes
  382
- Optional Integrated L2 Cache
  383
- Acp
  384
Chapter 8 Cache Protection

386
- Cache Protection Behavior
  387
- Error Reporting
  389
Chapter 9 Generic Interrupt Controller CPU Interface

391
- About the GIC CPU Interface
  391
- GIC Programmers Model
  392
Chapter 10 Generic Timer

399
- About the Generic Timer
  399
- Generic Timer Functional Description
  400
- Generic Timer Register Summary
  401
Chapter 11 Debug

404
- About Debug
  404
- Debug Register Interfaces
  406
- Aarch64 Debug Register Summary
  408
- Aarch64 Debug Register Descriptions
  410
- Aarch32 Debug Register Summary
  417
- Aarch32 Debug Register Descriptions
  419
- Memory-Mapped Register Summary
  423
- Memory-Mapped Register Descriptions
  427
- Debug Events
  438
- 11.10 External Debug Interface
  439
- 11.11 ROM Table
  443
Chapter 12 Performance Monitor Unit

456
- About the PMU
  456
- PMU Functional Description
  457
- Aarch64 PMU Register Summary
  459
- Aarch64 PMU Register Descriptions
  461
- Aarch32 PMU Register Summary
  468
- Aarch32 PMU Register Descriptions
  470
- Memory-Mapped Register Summary
  477
- Memory-Mapped Register Descriptions
  480
- Events
  490
- 12.10 Interrupts
  494
- 12.11 Exporting PMU Events
  495
Chapter 13 Embedded Trace Macrocell

497
- About the ETM
  497
- ETM Trace Unit Generation Options and Resources
  498
- ETM Trace Unit Functional Description
  500
- Processor Interface
  500
- Reset
  502
- Modes of Operation and Execution
  503
- ETM Trace Unit Register Interfaces
  504
- ETM Register Summary
  505
- ETM Register Descriptions
  508
- Interaction with Debug and Performance Monitoring Unit
  571
Chapter 14 Cross Trigger

572
- About the Cross Trigger
  573
- Trigger Inputs and Outputs
  574
- Cortex-A53 CTM
  575
- Cross Trigger Register Summary
  576
- Cross Trigger Register Descriptions
  579
Appendix A Signal Descriptions

589
- About the Signal Descriptions
  590
- Clock Signals
  591
- A.2 Clock Signals
  591
- Reset Signals
  592
- A.3 Reset Signals
  592
- Configuration Signals
  593
- A.4 Configuration Signals
  593
- Generic Interrupt Controller Signals
  594
- Generic Timer Signals
  596
- Power Management Signals
  597
- L2 Error Signals
  599
- A.8 L2 Error Signals
  599
- ACE and CHI Interface Signals
  600
- CHI Interface Signals
  601
- ACE Interface Signals
  605
- ACP Interface Signals
  610
- External Debug Interface
  613
- ATB Interface Signals
  616
- Miscellaneous ETM Trace Unit Signals
  617
- CTI Interface Signals
  618
- PMU Interface Signals
  619
- DFT and MBIST Interface Signals
  620
- Use of R15 by Instruction
  621
- Unpredictable Instructions Within an IT Block
  621
- Load/Store Accesses Crossing Page Boundaries
  622
- Armv8 Debug Unpredictable Behaviors
  622
- Other Unpredictable Behaviors
  622
  - B.1 Use of R15 by Instruction
    623
  - B.3 Load/Store Accesses Crossing Page Boundaries
    625
Appendix B Cortex-A53 Processor Aarch32 Unpredictable Behaviors

632
Appendix C Revisions

632

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