Figure 17-2 Tpiu Block Diagram (Etm Version) - ARM Cortex-M3 Technical Reference Manual

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Table of Contents

Trace Port Interface Unit

ATCLK Domain

TPIU components

Asynchronous

Asynchronous

A description of the main components of the TPIU is given in the following sections:

Asynchronous FIFO

Trace out on page 17-5

Advanced Trace Bus interface on page 17-5

Advanced Peripheral Bus interface on page 17-5.

Asynchronous FIFO

The asynchronous FIFO enables trace data to be driven out at a speed that is not

dependent on the speed of the core clock.

The formatter inserts source ID signals into the data packet stream so that trace data can

be re-associated with its trace source. The formatter is always active when the

TRACEPORT mode is active.

Figure 17-2 TPIU block diagram (ETM version)

TRACECLKIN Domain

(serializer)

ARM DDI 0337G