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Signal Descriptions
A.3
Miscellaneous
Name
LOCKUP
CURRPRI[7:0]
HALTED
DBGRESTARTED
TXEV
TRCENA
INTERNALSTATE[148:0]
BIGEND
EDBGRQ
PPBLOCK[5:0]
STCLK
STCALIB[25:0]
RXEV
VECTADDR[9:0]
A-4
Table A-3 lists the leftover signals.
Direction
Description
Output
LOCKUP gives immediate indication of seriously errant kernel software.
This is the result of the core being locked up because of an unrecoverable
exception following the activation of the processor's built in system state
protection hardware. For more information about the ARMv7-M
architectural lock up conditions see the ARMv7-M Architecture Reference
Manual.
Output
Indicates what priority interrupt (or base boost) is currently used.
CURRPRI represents the pre-emption priority, and does not indicate the
secondary priority.
Output
In halting debug mode. HALTED remains asserted while the core is in
debug.
Output
Handshake for DBGRESTART.
Output
Event transmitted as a result of SEV instruction. This is a single cycle pulse.
Output
Trace Enable. This signal reflects the setting of bit [24] of the Debug
Exception and Monitor Control Register. This signal gate the clock to the
TPIU and ETM blocks to reduce power consumption when trace is
disabled.
Output
Internal state.
Input
Static endian select:
1 = big-endian
0 = little-endian
This signal is sampled at reset, and cannot be changed when reset is
inactive.
Input
External debug request.
Input
Reserved. Must be tied to 6'b000000.
Input
System Tick Clock.
Input
System Tick Calibration.
Input
Causes a wakeup from a WFE instruction.
Input
Reserved. Must be tied to 10'b0000000000.
Copyright © 2005-2008 ARM Limited. All rights reserved.
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Table A-3 Miscellaneous signals
ARM DDI 0337G
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