Table 14-1 Instruction Fetches; Icode Bus Interface - ARM Cortex-M3 Technical Reference Manual

14.2

ICode bus interface

32-bit 32-bit
instruction instruction
fetch [31:16] fetch [15:0]
Thumb[15:0] Thumb[15:0]
Thumb-2[31:16] Thumb-2[15:0]
Thumb-2[15:0] Thumb-2[31:16]
ARM DDI 0337B
The ICode interface is a 32-bit AHBLite bus interface. Instruction fetches and vector
fetches from Code memory space (
bus.
Only the CM3Core instruction fetch bus can access the ICode interface, enabling
optimal code fetch performance. All fetches are word wide. The number of instructions
fetched per word depends on the code running and the alignment of the code in memory.
This is described in Table 14-1.
Description
All Thumb instructions are halfword aligned in memory, so two Thumb
instructions are fetched at a time. For sequential code, an instruction fetch is
performed every second cycle. Instruction fetches can be performed on
back-to-back cycles if there is an interrupt or a branch.
If Thumb-2 code is word-aligned in memory, then a complete Thumb-2
instruction is fetched each cycle.
If Thumb-2 code is halfword aligned, then the first 32-bit fetch only returns the
first halfword of the Thumb-2 instruction. A second fetch must be performed
to fetch the second halfword. This scenario creates a wait cycle (a cycle where
CM3Core is not able to execute an instruction) depending on the instruction in
play. The additional cycle of latency only occurs for the first halfword aligned
Thumb-2 instruction fetch. CM3Core contains a 3-entry fetch buffer, and so the
upper halfword of halfword aligned Thumb-2 instructions exist in the fetch
buffer for subsequent sequential Thumb-2 instructions.
All ICode instruction fetches are marked as cacheable and bufferable (HPROTI[3:2] =
2'b11), and as non-allocate and non-shareable (MEMATTRI = 2'b00). These attributes
are hard wired. If an MPU is fitted, the MPU region attributes are ignored for the ICode
bus.
HPROTI[0] indicates what is being fetched:
• 0 - instruction fetch
• 1 - vector fetch.
All ICode transactions are performed as non-sequentials.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
0x00000000 - 0x1FFFFFFF

Table 14-1 Instruction fetches

Bus Interface
) are performed over this
14-3