Table 17-15 Integration Register : Fifo Data 1 Bit Assignments; Figure 17-13 Integration Register : Fifo Data 1 Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
ARM DDI 0337G
30 29 28 27 26
25 24 23
Write point 1
ATVALID1S
Write point 2
ATVALID2S
Reserved

Figure 17-13 Integration register : FIFO data 1 bit assignments

Table 17-15 lists the bit assignments of the Integration register : FIFO data 0.

Table 17-15 Integration register : FIFO data 1 bit assignments

Bits Field
[31:30] -
[29] ATVALID2S
[28:27] Write point 2
[26] ATVALID1S
[25:24] Write point 1
[23:16] FIFO2 data 2
[15:8] FIFO2 data 1
[7:0] FIFO2 data 0
CoreSight specific registers
This section describes the CoreSight specific registers.
Claim Tag Clear Register
The register address, access type, and Reset state are:
Address
0xE0040FA4
Access Read/write
Reset state
0x0
This register forms one half of the Claim Tag value. This location enables individual bits
to be cleared, write, and returns the current Claim Tag value, read.
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16 15
FIFO2 data 2 FIFO2 data 1
Function
Reserved
Trace Port Interface Unit
0
8 7
FIFO2 data 0
17-19