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Embedded Trace Macrocell Interface
Branch Instruction
POP {PC}
POP {PC}
TBB/TBH
15-8
Table 15-3 Branches and stages evaluated by the processor (continued)
Instruction size
Stage branch target is issued
16 bits
Execute
32 bits
Execute
32 bits
Execute
Note
•
The encoding b1000 is only asserted in the cycle after conditional decode
branches if the branch is taken. This is a registered output, so could be used to
drive a multiplexor of addresses in the memory controller.
•
Multicycle LSU in the b0101 encoding suppresses fetches during execute because
it is known that the unconditional branch is executed so sequential fetches are
prevented.
•
Encodings are present for the multicycle duration of the decode, not only when
decode enable is asserted.
Speculative fetches might be cancelled during wait states. This means that the fetch
address might change to a new address while HREADY is low. See AMBA 3
compliance on page 12-3.
Figure 15-1 and Figure 15-2 on page 15-9 show a conditional branch backwards not
taken and taken. The branch occurs speculatively in the decode phase of the opcode.
The branch target is a halfword unaligned 16-bit opcode.
Copyright © 2005-2008 ARM Limited. All rights reserved.
HCLK
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT
0001
HTRANSI
NONSEQ
HADDRI
Figure 15-1 Conditional branch backwards not taken
Non-Confidential
Notes
-
-
-
0000
Fetch ahead of
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