Figure 8-7 Interrupt Priority Registers 0-31 Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
E000E400
E000E404
E000E408
E000E40C
E000E410
E000E414
E000E418
E000E41C
ARM DDI 0337G
Unrestricted Access
Interrupt Priority Registers
Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the
available interrupts. 0 is the highest priority, and 255 is the lowest.
The priority registers are stored with the implemented values first. This means that if
there are four bits of priority, the priority value is stored in bits [7:4] of the byte.
However, if there are three bits of priority, the priority value is stored in bits [7:5] of the
byte. This means that an application can work even if it does not know how many
priorities are possible.
The register address, access type, and Reset state are:
Address
0xE000E400
Access Read/write
Reset state
0x00000000
Figure 8-7 shows the bit assignments of Interrupt Priority Registers 0-7 for interrupts
0-31.
24 23
PRI_3
PRI_7
PRI_11
PRI_15
PRI_19
PRI_23
PRI_27
PRI_31
The lower PRI_n bits can specify subpriorities for priority grouping. See Exception
priority on page 5-6.
Copyright © 2005-2008 ARM Limited. All rights reserved.
-
0xE000E41F
16 15
PRI_2
PRI_6
PRI_10
PRI_14
PRI_18
PRI_22
PRI_26
PRI_30

Figure 8-7 Interrupt Priority Registers 0-31 bit assignments

Non-Confidential
Nested Vectored Interrupt Controller
8 7
PRI_1
PRI_5
PRI_9
PRI_13 PRI_12
PRI_17 PRI_16
PRI_21 PRI_20
PRI_25 PRI_24
PRI_29 PRI_28
0
PRI_0
PRI_4
PRI_8
8-17