Table 12-9 Target Response Summary For Dp Write Transaction Requests - ARM Cortex-M3 Technical Reference Manual

Sticky
ADDR [3:2]
flag set?
b00 X
Not b00 No
Not b00 No
Not b00 Yes
a. Writes might be accepted when other transactions are still outstanding, These writes might be abandoned subsequently.
See Access Port write buffering on page 12-32 for more information.
b. See Sticky overrun behavior on page 12-30 for details of data phase when overrun detection is enabled.
ARM DDI 0337B

Table 12-9 Target response summary for DP write transaction requests

SW-DP (target) response
AP
Ready?
ACK
X OK
a OK
Yes
No WAIT
X FAUL
T
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Action
Write WDATA value to ABORT Register.
Write WDATA value to DP register indicated by ADDR[3:2].
No data phase, unless overrun detection is enabled
No data phase, unless overrun detection is enabled
Debug Port
b
.
b
.
12-35