Table 8-26 Debug Fault Status Register Bit Assignments; Figure 8-21 Debug Fault Status Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

31
Bits Field
[31:5] -
[4] EXTERNAL
[3] VCATCH
ARM DDI 0337G
Unrestricted Access
The register address, access type, and Reset state are:
Address
0xE000ED30
Access Read/write-one-to-clear
Reset state
0x00000000
Figure 8-21 shows the bit assignments of the Debug Fault Status Register.
Table 8-26 describes the bit assignments of the Debug Fault Status Register.
Function
Reserved
External debug request flag:
1 = EDBGRQ signal asserted
0 = EDBGRQ signal not asserted.
The processor stops on next instruction boundary.
Vector catch flag:
1 = vector catch occurred
0 = no vector catch occurred.
When the VCATCH flag is set, a flag in one of the local fault status registers is also set to
indicate the type of fault.
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Figure 8-21 Debug Fault Status Register bit assignments

Table 8-26 Debug Fault Status Register bit assignments

Non-Confidential
Nested Vectored Interrupt Controller
5 4 3 2 1 0
EXTERNAL
VCATCH
DWTTRAP
BKPT
HALTED
8-39