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Name of register
ISAR4: ISA Feature register4
Software Trigger Interrupt Register
Peripheral identification register (PID4)
Peripheral identification register (PID5)
Peripheral identification register (PID6)
Peripheral identification register (PID7)
Peripheral identification register Bits [7:0] (PID0)
Peripheral identification register Bits [15:8] (PID1)
Peripheral identification register Bits [23:16] (PID2)
Peripheral identification register Bits [31:24] (PID3)
Component identification register Bits [7:0] (CID0)
Component identification register Bits [15:8] (CID1)
Component identification register Bits [23:16] (CID2)
Component identification register Bits [31:24] (CID3)
a. Reset value depends on the number of interrupts defined.
3.1.2
Core debug registers
ARM DDI 0337G
Unrestricted Access
Table 3-2 gives a summary of the core debug registers. For a detailed description of the
core debug registers, see Chapter 10 Core Debug.
Name of register
Debug Halting Control and Status Register
Debug Core Register Selector Register
Debug Core Register Data Register
Debug Exception and Monitor Control Register.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Type
Read-only
Write Only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read Only
Read-only
Read-only
Read-only
Type
Read/Write
Write-only
Read/Write
Read/Write
Non-Confidential
Table 3-1 NVIC registers (continued)
Address
0xE000ED70
0xE000EF00
0xE000EFD0
0xE000EFD4
0xE000EFD8
0xE000EFDC
0xE000EFE0
0xE000EFE4
0xE000EFE8
0xE000EFEC
0xE000EFF0
0xE000EFF4
0xE000EFF8
0xE000EFFC
Table 3-2 Core debug registers
Address
0xE000EDF0
0xE000EDF4
0xE000EDF8
0xE000EDFC
System Control
Reset value
0x01310102
-
0x04
0x00
0x00
0x00
0x00
0xB0
0x2B
0x00
0x0D
0xE0
0x05
0xB1
Reset Value
a
0x00000000
-
-
b
0x00000000
3-5
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