Table 15-4 Example Of An Opcode Sequence; Figure 15-7 Unconditional Branch In Execute Aligned; Figure 15-8 Unconditional Branch In Execute Unaligned - ARM Cortex-M3 Technical Reference Manual

ARM DDI 0337G
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HCLK
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT
HTRANSI
HADDRI
HCLK
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT 0101
HTRANSI NONSEQ
HADDRI
Table 15-4 shows an example of an opcode sequence.
Execute cycle
1
2
3
4
5
6
7
8
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0101
NONSEQ NONSEQ

Figure 15-7 Unconditional branch in execute aligned

NONSEQ NONSEQ

Figure 15-8 Unconditional branch in execute unaligned

Table 15-4 Example of an opcode sequence

Fetch address
0x1020
0x1022
0x1024
0x1026
0x1028
0x1040
0x1042
0x1044
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Embedded Trace Macrocell Interface
0000
NONSEQ NONSEQ NONSEQ
0000
NONSEQ NONSEQ NONSEQ
Opcode
ADD r1,#1
LDR r3,[r4]
ADD r2,#3
CMP r3,r2
BEQ = Target1
CMP r1,r2
// folded
ITE EQ
// skipped
LDR EQ r3,[r4,r1]
15-11