Table 2-3 Bit Functions Of The Epsr; Figure 2-4 Execution Program Status Register - ARM Cortex-M3 Technical Reference Manual

Programmer's Model
31
Field Name
[31:27] -
[26:25], [15:10] ICI
[26:25], [15:10] IT
[24] T
[23:16] -
[9:0] -
2-8
Note
Because the ICI field and the IT field overlap, load or store multiples within an If-Then
block cannot be interrupt-continued.
Figure 2-4 shows the bit assignments of the EPSR.
27 26 25 24 23
Reserved ICI/IT T
The EPSR is not directly accessible. Two events can modify the EPSR:
• an interrupt occurring during an LDM or STM instruction
• execution of the If-Then instruction.
Table 2-3 describes the bit assignments of the EPSR.
Definition
Reserved.
Interruptible-continuable instruction bits. When an interrupt occurs during an LDM or STM
operation, the multiple operation stops temporarily. The EPSR uses bits [15:12] to store the
number of the next register operand in the multiple operation. After servicing the interrupt,
the processor returns to the register pointed to by [15:12] and resumes the multiple
operation.
If-Then bits. These are the execution state bits of the If-Then instruction. They contain the
number of instructions in the if-then block and the conditions for their execution.
The T-bit can be cleared using an interworking instruction where bit [0] of the written PC
is 0. It can also be cleared by unstacking from an exception where the stacked T bit is 0.
Executing an instruction while the T bit is clear causes an INVSTATE exception.
Reserved.
Reserved.
Copyright © 2005-2008 ARM Limited. All rights reserved.
16 15
Reserved

Figure 2-4 Execution Program Status Register

Non-Confidential
10 9
ICI/IT Reserved

Table 2-3 Bit functions of the EPSR

0
ARM DDI 0337G
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