Figure 5-2 Exception Entry Timing - ARM Cortex-M3 Technical Reference Manual

CLK
INTISR[2]
HADDRS[31:0]
HWDATAS[31:0]
HADDRI[31:0]
HRDATAI[31:0]
CURRPRI[7:0]
ETMINSTAT[2:0]
ETMINTNUM[8:0]
ARM DDI 0337G
Unrestricted Access
1 2 3 4 5
SP+18
SP+1C
100
Twelve-cycle ISR entry latency
000
The NVIC indicates to the processor core, in the cycle after INTISR[2] was received,
that an interrupt has been received, and the processor initiates the stack push and vector
fetch in the following cycle.
When the stack push has completed, the first instruction of the ISR enters the execute
stage of the pipeline. In the cycle that the ISR enters execute:
• ETMINSTAT[2:0] indicates that the ISR has been entered (3'b001). This is a
1-cycle pulse.
• CURRPRI[7:0] indicates the priority of the active interrupt. CURRPRI remains
asserted throughout the duration of the ISR. CURRPRI becomes valid when
ETMINTSTAT indicates that the ISR has been entered (3'b001).
• ETMINTNUM[8:0] indicates the number of the active interrupt.
ETMINTNUM remains asserted throughout the duration of the ISR.
ETMINTNUM becomes valid when ETMINTSTAT indicates that the ISR has
been entered (3'b001). Prior to that it indicates which ISR is being fetched.
Figure 5-2 shows that there is a 12-cycle latency from asserting the interrupt to the first
instruction of the ISR executing.
Copyright © 2005-2008 ARM Limited. All rights reserved.
6 7 8 9
SP+0 SP+8
SP+4 SP+C
PC r0 r1 r2
xPSR
100 104 108
ISR fetch
100
18
Non-Confidential
10 11 12 13
SP+10
SP+14
r3 r12 LR
First ISR instruction
in Execute stage
001

Figure 5-2 Exception entry timing

Exceptions
14 15
Handler fetch
2
000
18
5-13