Pre-Emption; Figure 5-1 Stack Contents After A Pre-Emption - ARM Cortex-M3 Technical Reference Manual

Exceptions
5.5

Pre-emption

5.5.1 Stacking
5-10
The following sections describe the behavior of the processor when it takes an
exception:
• Stacking
• Late-arriving on page 5-14
• Tail-chaining on page 5-13.
When the processor invokes an exception, it automatically pushes the following eight
registers to the stack (SP) in the following order:
• PC
• xPSR
• r0-r3
• r12
• LR.
The SP is decremented by eight words by the completion of the stack push. Figure 5-1
shows the contents of the stack after an exception pre-empts the current program flow.
Note
Figure 5-1 shows the order on the stack.
After returning from the ISR, the processor automatically pops the eight registers from
the stack. Interrupt return is passed as a data field in the LR, so ISR functions can be
normal C/C++ functions, and do not require a veneer.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Old SP
SP

Figure 5-1 Stack contents after a pre-emption

<previous>
xPSR
PC
LR
r12
r3
r2
r1
r0
ARM DDI 0337B