Table 11-12 Dwt Lsu Count Register Bit Assignments; Figure 11-9 Dwt Lsu Count Register Bit Assignments; Figure 11-10 Dwt Fold Count Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

Field Name Definition
[31:8] - Reserved.
[7:0] LSUCNT LSU counter. This counts the total number of cycles that the processor is processing an LSU
operation. The initial execution cost of the instruction is not counted.
For example, an LDR which takes two cycles to complete increments this counter one cycle.
Equivalently, an LDR which stalls for two cycles (and so takes four cycles), increments this counter
three times. An event is emitted on counter overflow (every 256 cycles).
Clears to 0 on enabling.
ARM DDI 0337B
Figure 11-9 describes the fields of the DWT LSU Count Register.
Table 11-12 describes the fields of the DWT LSU Count Register.
DWT Fold Count Register
Use the DWT Fold Count Register to count the total number of folded instructions. This
counts 1 for each instruction which takes 0 cycles.
The register address, access type, and Reset state are:
Address
0xE0001018
Access Read/write
Reset state
-
Figure 11-10 describes the fields of the DWT Fold Count Register.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 11-9 DWT LSU Count Register bit assignments

Table 11-12 DWT LSU Count Register bit assignments

Figure 11-10 DWT Fold Count Register bit assignments

System Debug
11-21