Ahb Trace Macrocell Interface; Table A-13 Htm Interface - ARM Cortex-M3 Technical Reference Manual

Signal Descriptions
A.13

AHB Trace Macrocell interface

Name
HTMDHADDR[31:0]
HTMDHTRANS[1:0]
HTMDHSIZE[1:0]
HTMDHBURST[2:0]
HTMDHPROT[3:0]
HTMDHWDATA[31:0]
HTMDHWRITE
HTMDHRDATA[31:0]
HTMDHREADY
HTMDHRESP[1:0]
A-16
Table A-13 lists the signals of the AHB Trace Macrocell (HTM) interface
Direction Description
Output 32-bit address
Output Output indicates the type of the current data transfer. Can be IDLE,
NONSEQUENTIAL, OR SEQUENTIAL.
Output Indicates the size of the access. Can be 8, 16, or 32 bits.
Output Output indicates if the transfer is part of a burst.
Output Provides information on the access.
Output 32-bit write data bus.
Output Write not read.
Output Read data bus.
Output Ready signal.
Output The transfer response status. OKAY or ERROR.
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Table A-13 HTM interface

ARM DDI 0337G
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