Table 8-9 Bit Functions Of The Interrupt Set-Pending Register - ARM Cortex-M3 Technical Reference Manual

Nested Vectored Interrupt Controller
Field Name
[31:0] SETPEND
8-14
Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt
Set-Pending Register bit pends the corresponding interrupt.
Clear an Interrupt Set-Pending Register bit by writing a 1 to the corresponding bit in the
Interrupt Clear-Pending Register (see Interrupt Clear-Pending Register). Clearing the
Interrupt Set-Pending Register bit puts the interrupt into the non-pended state.
Note
Writing to the Interrupt Set-Pending Register has no affect on an interrupt that is already
pending or is disabled.
The register address, access type, and Reset state are:
Address
0xE000E200
Access Read/write
Reset state
0x00000000
Table 8-9 describes the field of the Interrupt Set-Pending Register.

Table 8-9 Bit functions of the Interrupt Set-Pending Register

Definition
Interrupt set-pending bits:
1 = pend the corresponding interrupt
0 = corresponding interrupt not pending.
Writing 0 to a SETPEND bit has no effect. Reading the bit returns its current state.
Interrupt Clear-Pending Register
Use the Interrupt Clear-Pending Register to:
• clear pending interrupts
• determine which interrupts are currently pending.
Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt
Clear-Pending Register bit puts the corresponding pending interrupt in the inactive
state.
Note
Writing to the Interrupt Clear-Pending Register has no effect on an interrupt that is
active unless it is pending as well.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
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0xE000E21C
ARM DDI 0337B