Table 14-1 Etm Core Interface Inputs And Outputs; Table 14-2 Miscellaneous Configuration Inputs - ARM Cortex-M3 Technical Reference Manual

Embedded Trace Macrocell
Name
ETMIA[31:1]
ETMIVALID
ETMDVALID
ETMICCFAIL
ETMIBRANCH
ETMIINDBR
ETMFLUSH
ETMISTALL
ETMFINDBR
ETMINTSTAT[2:0]
ETMINTNUM[8:0]
ETMCANCEL
COREHALT
DWTMATCH [3:0]
DWTINOTD[3:0]
14-4
• Advanced Peripheral Bus (APB) interface signals. See Table 14-6 on page 14-6.
Description
Core instruction address bus.
Current instruction data represents an instruction.
Current instruction data represents an instruction.
Instruction failed its condition code.
Instruction is a branch target.
Instruction is an indirect branch target.
PC modified before next instruction.
Indicates that the last instruction signalled by the core has not
yet entered execute.
PC modified by an indirect operation.
Exception entry and exit.
Exception type.
Exception is a canceling exception.
Core is halted.
Indicates that the Data Watchpoint and Trace (DWT) trigger
units have matched the conditions currently present on the
address, data and control buses.
Indicates that the DWT trigger units are performing
comparisons on PC value (set) or data address (clear).
Name Description
NIDEN Non invasive debug enable
EXTIN[1:0] External input resource
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Table 14-1 ETM core interface inputs and outputs

Table 14-2 Miscellaneous configuration inputs

Non-Confidential
Qualified by Direction
ETMIVALID Input
- Input
- Input
ETMIVALID Input
ETMIVALID Input
ETMIBRANCH Input
- Input
- Input
ETMFLUSH Input
- Input
ETMINTSTAT Input
ETMINTSTAT Input
- Input
- Input
- Input
Direction Clock domain
Input FCLK
Input FCLK
ARM DDI 0337G
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