Table of Contents
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Preface
About this book
Product revision status
Intended audience
Using this book
xx
This book is for the Cortex-M3 processor.
The rnpn identifier indicates the revision status of the product described in this manual,
where:
rn
Identifies the major revision of the product.
pn
Identifies the minor revision or modification status of the product.
This manual is written to help system designers, system integrators, and verification
engineers who are implementing a System-on-Chip (SoC) device based on the
Cortex-M3 processor.
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for a description of the components of the processor, and about
the processor instruction set.
Chapter 2 Programmer's Model
Read this for a description of the processor register set, modes of
operation, and other information for programming the processor.
Chapter 3 System Control
Read this for a description of the registers and programmer's model for
system control.
Chapter 4 Memory Map
Read this for a description of the processor memory map and bit-banding
feature.
Chapter 5 Exceptions
Read this for a description of the processor exception model.
Chapter 6 Clocking and Resets
Read this chapter for a description of the processor clocking and resets.
Copyright © 2005-2008 ARM Limited. All rights reserved.
Non-Confidential
ARM DDI 0337G
Unrestricted Access
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Table of Contents
