Table 17-2 Atb Port Signals; Table 17-3 Miscellaneous Configuration Inputs - ARM Cortex-M3 Technical Reference Manual

Trace Port Interface Unit
Name Type
CLK Input
nRESET Input
CLKEN Input
ATVALID1S Input
ATREADY1S Output
ATDATA1S[7:0] Input
ATID1S[6:0] Input
ATVALID2S Input
ATREADY2 Output
ATDATA2S[7:0] Input
ATID2S[6:0] Input
Name
MAXPORTSIZE[1:0]
SyncReq
TRIGGER
17-6
Advanced Trace Bus interface
There is one or two ATB interfaces depending on the TPIU configuration. Table 17-2
describes the ATB port signals. The signals for port 2 are not used when the TPIU is
configured with a single ATB interface.
Description
Trace bus and APB interface clock.
Reset for the CLK domain (ATB/APB interface).
Clock enable for CLK domain.
Data from trace source 1 is valid in this cycle.
If this signal is asserted (ATVALID high), then the data was accepted this cycle from trace
source 1.
Trace data input from source 1.
Trace source ID for source 1. This must not change dynamically.
Data from trace source 2 is valid in this cycle.
If this signal is asserted (ATVALID high), then the data was accepted this cycle from trace
source 2.
Trace data input from source 2.
Trace source ID for source 2. This must not change dynamically.
Miscellaneous configuration inputs
Table 17-3 describes the miscellaneous configuration inputs.
Type Description
Input Defines the maximum number of pins available for synchronous trace output.
Input Global trace synchronization trigger. Inserts synchronization packets into the
formatted data stream. Only used when the formatter is active. This signal must be
connected to the DSYNC output from Cortex-M3.
Input Causes a trigger packet to be inserted into the trace stream when the formatter is
active.
Copyright © 2005-2008 ARM Limited. All rights reserved.

Table 17-2 ATB port signals

Table 17-3 Miscellaneous configuration inputs

ARM DDI 0337G