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5.7
Late-arriving
1
CLK
INTISR[2]
INTISR[8]
INTISR[9]
HADDRS[31:0]
HWDATAS[31:0]
HADDRI[31:0]
HRDATAI[31:0]
CURRPRI[7:0]
ETMINSTAT[2:0]
000
ETMINTNUM[8:0]
ARM DDI 0337G
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A late-arriving interrupt can pre-empt a previous interrupt if the first instruction of the
previous ISR has not entered the Execute stage, and the late-arriving interrupt has a
higher priority than the previous interrupt.
A late-arriving interrupt causes a new vector address fetch and ISR prefetch. State
saving is not performed for the late-arriving interrupt because it has already been
performed for the initial interrupt and so does not have to be repeated.
Figure 5-4 shows an example of late-arriving interrupts.
2
3
4
5
6
7
8
SP+18
SP+0
SP+8
SP+1C
SP+4
PC
r0 r1 r2
xPSR
100
104 108
100
Fetch of
ISR6
018
In Figure 5-4, INTISR[8] pre-empts INTISR[2]. The state saving for INTISR[2] is
already done and is not required to be repeated. Figure 5-4 shows the latest point at
which INTISR[8] can pre-empt before the first instruction of the ISR for INTISR[2]
enters Execute stage. A higher priority interrupt after that point is managed as a
pre-emption.
Copyright © 2005-2008 ARM Limited. All rights reserved.
9
10 11
12
13 14 15 16
SP+10
SP+C
SP+14
r3
r12
LR
500 504
500
Fetch of
ISR12
FF
100
024
Figure 5-4 Late-arriving exception timing
Non-Confidential
17 18
19
20 21
600 604 608
600
Fetch of
ISR15
8-cycle ISR entry
First ISR instruction
latency
is in Execute stage
025
Exceptions
22 23
24
25
09
001
000
5-15
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