Table 12-12 Terms Used In Sw-Dp Timing; Figure 12-15 Sw-Dp Acknowledgement Timing - ARM Cortex-M3 Technical Reference Manual

Debug Port
12-38
An access port access results in the generation of a transfer on the DAP internal bus.
These transfers have an address phase and a data phase. The data phase can be extended
by the access if it requires extra time to process the transaction, for example, if it has to
perform an AHB access to the system bus to read data.
Table 12-12 shows the terms used in Figure 12-16 on page 12-39 to Figure 12-18 on
page 12-40.
Term
W.APACC
R.APACC
xxPACC
WD[0]
WD[-1]
WD[1]
RD[0]
RD[1]
Figure 12-16 on page 12-39 shows a sequence of write transfers. It shows that a single
new transfer, WD[1], can be accepted by the serial engine, while a previous write
transfer, WD[0], is completing. Any subsequent transfer must be stalled until the first
transfer completes.
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 12-15 SW-DP acknowledgement timing

Table 12-12 Terms used in SW-DP timing

Description
Write a DAP access port register.
Read a DAP access port register.
Read or write, to debug port or access port register.
First write packet data.
Previous write packet data. A transaction that happened
before the figures timeframe.
Second write packet data.
First read packet data.
Second read packet data.
ARM DDI 0337B