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ARM Cortex-R4F Technical Reference Manual

ARM Cortex-R4F Technical Reference Manual (456 pages)

Cortex-R4 and Cortex-R4F Technical Reference Manual

Brand: ARM | Category: Processor | Size: 2.99 MB

Table of Contents

Change History
2
Table of Contents
3
Preface

16
- About this Book
  17
- Key to Timing Diagram Conventions
  19
- Feedback
  21
Chapter 1 Introduction

23
Chapter 2 Programmer's Model

48
Chapter 3 Processor Initialization, Resets, and Clocking

76
- Initialization
  77
- Resets
  81
- Reset Modes
  82
- Table 3-1 Reset Modes
  82
- Figure 3-1 Power-On Reset
  82
- Clocking
  84
- Figure 3-2 AXI Interface Clocking
  84
Chapter 4 System Control Coprocessor

85
Chapter 5 Prefetch Unit

160
- About the Prefetch Unit
  160
- About the Prefetch Unit
  161
- Branch Prediction
  162
- Return Stack
  164
Chapter 6 Events and Performance Monitor

166
- About the Events
  166
  - Table 6-1 Event Bus Interface Bit Functions
    166
  - Table
    167
  - Table
    168
  - Table
    169
- About the PMU
  170
- Performance Monitoring Registers
  171
  - Figure 6-1 PMNC Register Format
    171
  - Table 6-2 PMNC Register Bit Functions
    171
  - Figure
    172
  - Table
    172
- Table 6-3 CNTENS Register Bit Functions
  173
- Figure 6-2 CNTENS Register Format
  173
- Table 6-4 CNTENC Register Bit Functions
  174
- Figure 6-3 CNTENC Register Format
  174
- Table 6-5 Overflow Flag Status Register Bit Functions
  175
- Figure 6-4 FLAG Register Format
  175
- Table 6-6 SWINCR Register Bit Functions
  176
- Figure 6-5 SWINCR Register Format
  176
- Figure 6-6 PMNXSEL Register Format
  176
- Table 6-7 Performance Counter Selection Register Bit Functions
  177
- Table 6-8 Evtselx Register Bit Functions
  178
- Figure 6-7 Evtselx Register Format
  178
- Table 6-9 USEREN Register Bit Functions
  179
- Figure 6-8 USEREN Register Format
  179
- Table 6-10 INTENS Register Bit Functions
  180
- Figure 6-9 INTENS Register Format
  180
- Table 6-11 INTENC Register Bit Functions
  181
- Figure 6-10 INTENC Register Format
  181
- Event Bus Interface
  183
- Table
  183
Chapter 7 Memory Protection Unit

185
- About the MPU
  185
  - Table 7-1 Default Memory Map
    185
  - Table
    186
  - Figure
    187
  - Table
    187
- Figure 7-1 Overlapping Memory Regions
  188
- Figure 7-2 Overlay for Stack Protection
  188
- Figure 7-3 Overlapping Subregion of Memory
  189
- Memory Types
  190
- Table 7-2 Memory Attributes Summary
  190
- Region Attributes
  192
- Table 7-3 TEX[2:0], C, and B Encodings
  192
- Table 7-4 Inner and Outer Cache Policy Encoding
  193
- MPU Interaction with Memory System
  194
- MPU Faults
  195
- MPU Software-Accessible Registers
  196
- Figure
  196
Chapter 8 Level One Memory System

198
Chapter 9 Level Two Interface

235
Chapter 10 Power Control

266
- About Power Control
  266
- About Power Control
  267
- Power Management
  268
Chapter 11 Debug

270
Chapter 12 FPU Programmer's Model

342
Chapter 13 Integration Test Registers

356
Chapter 14 Cycle Timings and Interlock Behavior

367
Chapter 15 AC Characteristics

401
Appendix A Processor Signal Descriptions

415
- About the Processor Signal Descriptions
  415
- Table
  415
- Global Signals
  416
- Table A-1 Global Signals
  416
- A.2 Global Signals
  416
- Configuration Signals
  417
- Table A-2 Configuration Signals
  417
  - A.3 Configuration Signals
    417
  - Table
    419
- Interrupt Signals, Including VIC Interface Signals
  420
- Table A-3 Interrupt Signals
  420
- L2 Interface Signals
  421
- Table A-4 AXI Master Port Signals for the L2 Interface
  421
- A.5 L2 Interface Signals
  421
- Table A-5 AXI Master Port Error Detection Signals
  423
- Table A-6 AXI Slave Port Signals for the L2 Interface
  423
- Table A-7 AXI Slave Port Error Detection Signals
  425
- TCM Interface Signals
  426
- Table A-8 ATCM Port Signals
  426
- Table A-9 B0TCM Port Signals
  426
- Table A-10 B1TCM Port Signals
  427
- Dual Core Interface Signals
  429
- Table A-11 Dual Core Interface Signals
  429
- Debug Interface Signals
  430
- Table A-12 Debug Interface Signals
  430
- Table A-13 Debug Miscellaneous Signals
  430
- ETM Interface Signals
  432
- Table A-14 ETM Interface Signals
  432
- Test Signals
  433
- Table A-15 Test Signals
  433
- A.10 Test Signals
  433
- MBIST Signals
  434
- Table A-16 MBIST Signals
  434
- A.11 MBIST Signals
  434
- Validation Signals
  435
- Table A-17 Validation Signals
  435
- A.12 Validation Signals
  435
- FPU Signals
  436
  - A.13 FPU Signals
    436
  - Table A-18 FPU Signals
    436
Appendix Becc Schemes

437
- ECC Scheme Selection Guidelines
  438
Appendix C Revisions

442
Glossary

442

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ARM Cortex-R4F Technical Reference Manual

ARM Cortex-R4F Technical Reference Manual (436 pages)

Brand: ARM | Category: Processor | Size: 3.06 MB

Table of Contents

Table of Contents
3
Preface

7
- About this Book
  8
  - Timing Diagrams
    10
  - Other Publications
    11
- Feedback
  12
Chapter 1 Introduction

14
- About the Processor
  14
- Compliance
  15
- Features
  16
- Interfaces
  17
- Configurable Options
  18
- Test Features
  22
- Product Documentation, Architecture and Design Flow
  23
- Product Revisions
  25
Chapter 2 Functional Description

26
- About the Functions
  27
  - Branch Prediction
    28
    
    Interrupt Handling
    31
    
    Exception Processing
    32
- Interfaces
  34
- Clocking and Resets
  36
- Normal Operation
  37
- Operation
  40
Chapter 3 Programmers Model

45
- About the Programmers Model
  45
- Modes of Operation and Execution
  46
- Memory Model
  47
- Data Structures
  48
- Registers
  49
  - Program Status Registers
    52
  - Exceptions
    57
    
    Interrupt Controller
    61
    
    Interrupt Entry Flowchart
    61
    
    Exception Vectors
    67
  - Acceleration of Execution Environments
    68
  - Unaligned and Mixed-Endian Data Access Support
    69
  - Big-Endian Instruction Support
    70
Chapter 4 System Control

71
- About System Control
  72
- System Validation
  75
- Register Summary
  77
- Register Descriptions
  79
- Invalidate and Clean Operations
  129
Chapter 5 Prefetch Unit

151
- About the Prefetch Unit
  151
- Branch Prediction
  153
- Return Stack
  154
- Controlling Instruction Prefetch and Program Flow Prediction
  156
Chapter 6 Events and Performance Monitor

157
- About the Events
  157
- About the PMU
  158
- Performance Monitoring Registers
  162
- Event Bus Interface
  175
Chapter 7 Memory Protection Unit

176
- About the MPU
  177
- Memory Types
  182
- Region Attributes
  183
- MPU Interaction with Memory System
  184
- MPU Faults
  185
- MPU Software-Accessible Registers
  186
Chapter 8 Level One Memory System

188
- About the L1 Memory System
  188
- About the Error Detection and Correction Schemes
  190
- Fault Handling
  193
- About the Tcms
  199
- About the Caches
  204
- Internal Exclusive Monitor
  220
- Memory Types and L1 Memory System Behavior
  221
- Error Detection Events
  222
Chapter 9 Level Two Interface

225
- About the L2 Interface
  225
- AXI Master Interface
  226
- Memory Attributes
  228
- AXI Master Interface Transfers
  230
- AXI Slave Interface
  243
- Enabling or Disabling AXI Slave Accesses
  246
- Accessing Rams Using the AXI Slave Interface
  247
Chapter 10 Power Control

257
- About Power Control
  257
- Power Management
  259
Chapter 11 FPU Programmers Model

262
- About the FPU Programmers Model
  262
- General-Purpose Registers
  263
- System Registers
  264
- Modes of Operation
  271
- Compliance with the IEEE 754 Standard
  272
Chapter 12 Debug

276
- Debug Systems
  276
- About the Debug Unit
  277
- Debug Register Interface
  279
- Debug Register Descriptions
  284
- Management Registers
  309
- Debug Events
  316
- Debug Exception
  318
- Debug State
  321
- Coprocessor Instructions
  324
- Cache Debug
  327
- External Debug Interface
  328
- Using the Debug Functionality
  331
- Debugging Systems with Energy Management Capabilities
  348
Chapter 13 Integration Test Registers

351
Signal Descriptions

359
Appendix A Signal Descriptions

360
- About the Processor Signal Descriptions
  360
- Global Signals
  361
- Configuration Signals
  362
- Interrupt Signals, Including VIC Interface Signals
  365
- L2 Interface Signals
  366
- TCM Interface Signals
  371
- Redundant Processor Signals
  374
- Debug Interface Signals
  375
- ETM Interface Signals
  377
- Test Signals
  378
- MBIST Signals
  379
- Validation Signals
  380
- FPU Signals
  381
Appendix B AC Characteristics

382
- Processor Timing
  382
- Processor Timing Parameters
  384
Appendix C Cycle Timings and Interlock Behavior

397
- About Cycle Timings and Interlock Behavior
  397
- Register Interlock Examples
  400
- Data Processing Instructions
  401
- QADD, QDADD, QSUB, and QDSUB Instructions
  403
- Media Data-Processing
  404
- Sum of Absolute Differences (SAD)
  405
- Multiplies
  406
- Divide
  408
- Branches
  409
- Processor State Updating Instructions
  410
- Single Load and Store Instructions
  411
- Load and Store Double Instructions
  414
- Load and Store Multiple Instructions
  415
- RFE and SRS Instructions
  418
- Synchronization Instructions
  419
- Coprocessor Instructions
  420
- SVC, BKPT, Undefined, and Prefetch Aborted Instructions
  421
- Miscellaneous Instructions
  422
- C.23 Dual Issue C
  428

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