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Embedded Trace Macrocell
14.6
ETM programmer's model
14.6.1
Advanced Peripheral Bus interface
14.6.2
List of ETM registers
Name
ETM Control
Configuration Code
Trigger Event
ASIC Control
ETM Status
System Configuration
14-16
The ETM programmer's model is described in detail in the ARM Embedded Trace
Macrocell Architecture Specification. This section defines the implementation-specific
features of the ETM programmer's model.
The ETM contains an APB slave interface that can read and write to the ETM registers.
This interface is synchronous to the processor clock. The core and the external debug
interface can access it through the Serial Wire Debug Port/JTAG Debug Port
(SW-DP/JTAG-DP).
The ETM registers are listed in Table 14-9. For full details, see the ARM Embedded
Trace Macrocell Architecture Specification.
Type
Read/write
Read only
Read/write
-
Read/write
Read only
Copyright © 2005-2008 ARM Limited. All rights reserved.
Address
Present
Yes
0xE0041000
Yes
0xE0041004
Yes
0xE0041008
No
0xE004100C
Yes
0xE0041010
Yes
0xE0041014
Non-Confidential
Table 14-9 ETM registers
Description
For a description, see page 14-19.
For a description, see page 14-20.
Defines the event that controls the
trigger.
[16:14] Boolean function.
[13:7] Resource A.
[6:0] Resource B
See ETM Event resources on
page 14-22.
-
Provides information on the
current status of the trace and
trigger logic.
[3] - Trigger Flag.
[2] - Start/Stop resource status.
[1] - Programming bit status.
[0] - Untraced Overflow.
For a description, see page
page 14-20.
ARM DDI 0337G
Unrestricted Access
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