Table 12-7 Target Response Summary For Dp Read Transaction Requests - ARM Cortex-M3 Technical Reference Manual

Hide thumbs Also See for Cortex-M3:
Table of Contents

Advertisement

ADDR
Sticky
[3:2]
flag set?
b00
X
b01
X
b10
No
b11
No
b10
No
ARM DDI 0337B
Note
If Pushed Verify or Pushed Compare is enabled, AP write transactions are converted
into AP reads. These are then treated in the same way as other AP read operations. See
Pushed compare and pushed verify operations on page 12-44 for details of these
operations.
If you have to perform an SW-DP read of the IDCODE or CTRL/STAT Register, or an
SW-DP write to the ABORT Register immediately after a sequence of AP writes, you
must first perform an access that the SW-DP is able to stall. In this way you can check
that the write buffer is lost before performing the SW-DP register access. If this is not
done, WDATAERR might be set, and the buffered writes lost.
Summary of target responses
Table 12-7 summarizes the target SW-DP response to all possible debugger DP read
operation requests.
Table 12-8 on page 12-34 summarizes the target SW-DP response to all possible
debugger AP read operation requests.
Table 12-9 on page 12-35 summarizes the target SW-DP response to all possible
debugger DP write operation requests, assuming the WDATA parity check is good.
Table 12-10 on page 12-36 summarizes the target SW-DP response to all possible
debugger AP write operation requests, assuming the WDATA parity check is good.
Fault conditions that are not shown in these two tables are described in Fault conditions
not included in the target response tables on page 12-36

Table 12-7 Target response summary for DP read transaction requests

SW-DP (target) response
AP
Ready?
ACK
Action
X
OK
Respond with IDCODE value.
X
OK
Respond with CRTL/STAT or WCR value
Yes
OK
Respond with RESEND value from previous AP read.
Yes
OK
Respond with RDBUF value from previous AP read, and set READOK
flag in CTRL/STAT Register.
No
WAIT
No data phase, unless overrun detection is enabled
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Debug Port
a
.
b
.
12-33

Advertisement

Table of Contents
loading

Table of Contents