Table 11-20 Bit Functions Of The Itm Trace Privilege Register; Figure 11-13 Itm Trace Privilege Register Bit Assignments - ARM Cortex-M3 Technical Reference Manual

ARM DDI 0337B
Note
Privileged writes are accepted to this register if ITMEN is set. User writes are accepted
to this register if ITMEN is set and the appropriate privilege mask is cleared. Privileged
access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots
or bandwidth as required.
ITM Trace Privilege Register
Use the ITM Trace Privilege Register to enable an operating system to control which
stimulus ports are accessible by user code.
Note
You can only write to this register in Privileged mode.
The register address, access type, and Reset state are:
Access Read/write
Address
0xE0000E40
Reset
0x00000000
Figure 11-13 shows the ITM Trace Privilege Register bit assignments.
Table 11-20 describes the fields of the ITM Trace Privilege Register.

Table 11-20 Bit functions of the ITM Trace Privilege Register

Field
[31:4]
[3:0]
Copyright © 2005, 2006 ARM Limited. All rights reserved.

Figure 11-13 ITM Trace Privilege Register bit assignments

Name Definition
- Reserved
Privilege Mask Bit mask to enable tracing on ITM stimulus ports:
bit[0] = stimulus ports [7:0]
bit[1] = stimulus ports [15:8]
bit[2] = stimulus ports [23:16]
bit[3] = stimulus ports [31:24].
System Debug
11-29