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ARM DDI 0337B
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means HIGH for
active-HIGH signals and LOW for active-LOW signals.
Lower-case n
Denotes an active-LOW signal.
Prefix H
Denotes Advanced High-performance Bus (AHB) signals.
Prefix P
Denotes Advanced Peripheral Bus (APB) signals.
Numbering
The numbering convention is:
<size in bits>'<base><number>
This is a Verilog method of abbreviating constant numbers. For example:
•
'h7B4 is an unsized hexadecimal value.
•
'o7654 is an unsized octal value.
•
8'd9 is an eight-bit wide decimal value of 9.
•
8'h3F is an eight-bit wide hexadecimal value of
equivalent to b00111111.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Key to timing diagram conventions
0x3F
Preface
. This is
xxi
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