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A.11
AHB-AP interface
Name
DAPRDATA[31:0]
DAPREADY
DAPSLVERR
DAPCLKEN
DAPEN
DAPADDR[31:0]
DAPSEL
DAPENABLE
DAPWRITE
DAPWDATA[31:0]
DAPABORT
FIXMASTERTYPE
ARM DDI 0337G
Unrestricted Access
Table A-11 lists the signals of the AHB-AP interface.
Direction
Description
Output
The read bus is driven by the selected AHB-AP during read cycles when
DAPWRITE is LOW.
Output
The AHB-AP uses this signal to extend a DAP transfer.
Output
The error response is because of:
•
Master port produced an error response, or transfer not initiated because of
DAPEN preventing a transfer.
•
Access to AP register not accepted after a DAPABORT operation.
Input
DAP clock enable (power saving).
Input
AHB-AP enable.
Input
DAP address bus.
Input
Select signal generated from the DAP decoder to each AP. This signal indicates that
the slave device is selected, and a data transfer is required. There is a DAPSEL
signal for each slave. The signal is not generated by the driving DP. The decoder
monitors the address bus and asserts the relevant DAPSEL.
Input
This signal indicates the second and subsequent cycles of a DAP transfer from DP
to AHB-AP.
Input
When HIGH indicates a DAP write access from DP to AHB-AP. When LOW
indicates a read access.
Input
The write bus is driven by the DP block during write cycles when DAPWRITE is
HIGH.
Input
Aborts the current transfer. The AHB-AP returns DAPREADY HIGH without
affecting the state of the transfer in progress in the AHB Master Port.
Input
Setting this signal to 1 overrides the MasterType bit of the AHB-AP Control and
Status Word (CSW). This ensures accesses from the debugger is always issued as
0x1
on HMASTERD and HMASTERS regardless of the MasterType setting in the
CSW.
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Signal Descriptions
Table A-11 AHB-AP interface
A-13
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