Table 12-2 Standard Ir Instructions - ARM Cortex-M3 Technical Reference Manual

Debug Port
IR instruction
value
b0xxx
b1000
b1001
b1010
b1011
b110x
b1110
b1111
12-8
The IR instructions
The description of the JTAG Instruction Register shows how a 4-bit instruction is
transferred into the IF. This instruction determines the physical Data Register that the
JTAG Data Register maps onto, as described in DR scan chain and DR registers on
page 12-10. The standard IR instructions are listed in Table 12-2, and recommended
implementation-defined extensions to this instruction set are described in
Implementation-defined extensions to the IR instruction set.
Unused IR instruction values select the Bypass register, described in The JTAG Bypass
Register (BYPASS) on page 12-10.
JTAG-DP DR scan
register width
- -
ABORT 35
- -
DPACC 35
APACC 35
- -
IDCODE 32
BYPASS 1
Implementation-defined extensions to the IR instruction set
The eight IR instructions b0000 to b0111 are reserved for Implementation-defined
extensions to the JTAG-DP. These registers might be used for accessing a boundary scan
register, for IEEE 1149.1 compliance. The required instructions are listed in Table 12-3
on page 12-9.
Note
• ARM Limited recommends that separate JTAG TAPs are used for boundary scan
and debug.
• If the IR register is set to an IR instruction value that is not implemented, or
reserved, then the Bypass Register is selected.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
See section
Implementation-defined extensions to the IR instruction set
The JTAG-DP Abort Register (ABORT) on page 12-18
-
The JTAG DP/AP Access Registers (DPACC/APACC) on page 12-11
-
The JTAG Device ID Code Register (IDCODE) on page 12-10
The JTAG Bypass Register (BYPASS) on page 12-10

Table 12-2 Standard IR instructions

ARM DDI 0337B