Table 17-12 Integration Mode Control Register Bit Assignments; Table 17-13 Integration Register : Trigger Bit Assignments; Figure 17-11 Integration Register : Trigger Bit Assignments - ARM Cortex-M3 Technical Reference Manual

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ARM DDI 0337G
Table 17-12 lists the bit assignments of the Integration Mode Control Register

Table 17-12 Integration Mode Control Register bit assignments

Integration Register: TRIGGER
The register address, access type, and Reset state are:
Address
0xE0040EE8
Access Read only
Reset state
0x0
Figure 17-11 shows the bit assignments of the Integration Register : TRIGGER.

Figure 17-11 Integration Register : TRIGGER bit assignments

Table 17-13 lists the bit assignments of the Integration Register : TRIGGER bit
assignments.

Table 17-13 Integration Register : TRIGGER bit assignments

Integration Register : FIFO data 0
The register address, access type, and Reset state are:
Address
0xE0040EEC
Access Read only
Copyright © 2005-2008 ARM Limited. All rights reserved.
Bits Field
[31:2] -
[1] FIFO test mode
[0] Integration test mode
Reserved
Bits Field
[31:1] -
[0] TRIGGER input value
Trace Port Interface Unit
Function
Reserved, SBZ
Enables FIFO test mode
Enables integration test mode
TRIGGER input value
Function
Reserved
Enables the TRIGGER input
1 0
17-17