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Debug Port
12-26
A WAIT response to a read or write packet request is shown in Figure 12-10 on
page 12-26.
Figure 12-10 Serial Wire Debug WAIT response to a packet request
Note
If Overrun Detection is enabled then a data phase is required on a WAIT response. For
more information see Sticky overrun behavior on page 12-30.
FAULT response to Read or Write operation request
A FAULT response to a read or write packet request consists of two phases:
•
an eight-bit read or write packet request, from the host to the target
•
a three-bit FAULT acknowledge response, from the target to the host.
By default, there are single-cycle turnaround periods between these two phases, and
after the second phase. See the description of Trn in Key to illustrations of operations
on page 12-22 for more information.
A FAULT response to a read or write packet request is shown in Figure 12-11.
Figure 12-11 Serial Wire Debug FAULT response to a packet request
Note
If Overrun Detection is enabled then a data phase is required on a FAULT response. For
more information see Sticky overrun behavior on page 12-30.
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
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